In the technical field of logic circuits, in particular, there is continually a desire for shorter switching times in order that the circuit operates faster overall. This increasingly leads to problems, particularly in the case of memory modules. Present-day memory modules are operated at a frequency of up to 400 MHz. Further frequency increases are envisaged for the next generations of memory modules. As the storage capacity increases at the same time, this results in extremely stringent requirements for the access time to an individual memory cell.
The fundamentally customary construction of a DRAM module is described in IEEE Journal of Solid-State Circuits, Vol. sc-20, No. 5, October 1985, pages 914 to 923. In the arrangement illustrated, a comparatively wide logic region is formed along a center axis. The logic region has, inter alia, so-called address multiplexers, address generators, read and write amplifiers, etc. Connection contacts, the so-called pads, are additionally arranged in this region. Word and bit lines are arranged in a rectangular grid on the chip. In addition to the logic region running in the longitudinal direction along the center axis, additional logic regions are provided at right angles thereto, which divide the chip into individual memory banks. Within such a memory bank, besides the individual word lines, an area for sense amplifiers is additionally arranged at a uniform distance, i.e., after a predetermined number of word lines.
As the number of memory cells continuously increases and the clock number simultaneously increases, it becomes more and more difficult to handle the access times to the individual memory cells. This means that reading from or writing to a memory cell that is arranged spatially close to the logic has to be effected just as reliably as for a memory cell that is arranged far away from the logic. As a result of the high different spatial distance, the propagation times differ greatly, however, so that at high clock rates and thus with low access times, a reliable, i.e., error-free, management of the accesses can be made possible only with a high technical outlay.
Even though the technical environment has been described on the basis of a DRAM chip hitherto, the same problem area nevertheless arises in the case of any other type of memory component, but in principle also in the case of any semiconductor arrangement in which a multiplicity of elements that are intended to be addressed with very precise timing are arranged with a high integration density.